This software-hardware co-design achieves significant NoC bandwidth savings and speedups in manycore processors, highlighting sharer exposure.
As the core counts continue to scale in manycore processors, the increasing bandwidth pressure on the network-on-chip (NoC) and last-level cache (LLC) emerges as a critical performance bottleneck. While shared-data multicasting from the LLC can alleviate this pressure by combining responses heading to the same direction, existing solutions face fundamental challenges in accurately identifying complete sharer sets and avoiding unnecessary data responses. In this work, we propose Software Prefetch Multicast (SPM), a software-hardware co-design that addresses these limitations through sharer-exposed prefetching for bandwidth-efficient multicast. SPM introduces three key innovations: (1) New software-hardware interfaces including sharer group configuration and sharer-exposed prefetching instructions, enabling software-directed multicast initiation; (2) A corresponding microarchitecture for sharer group configuration that supports sharer-group-based multicast triggering in LLC through representative prefetch requests from leader threads; and (3) A dynamic leader thread switching algorithm to accommodate thread variation. Compared with a system with software prefetching, SPM achieves an average of 42% NoC bandwidth saving, a geometric mean of 1.28 × and a maximum of 1.46 × speedup in a 16-core system. In a 64-core system, it can achieve an average of 50% NoC bandwidth saving, along with a geomean of 1.38 × and a maximum of 1.86 × speedup.
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Chen et al. (2025) studied this question.
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