The manufacturing processes of Printed Circuit Boards (PCBs) have become increasingly complex, and even minor defects can significantly impair product performance and yield. Accurate identification of PCB defects is therefore crucial but remains challenging. Given the low resolution, small target size, and diverse nature of PCB surface defects, this study proposes a novel YOLO MSES-SPDConv (MS-YOLO) network based on an improved YOLOv10 framework to achieve more accurate and efficient detection of minor PCB defects with a smaller model size. Firstly, to address the performance bottleneck of the C2F module in the head network of YOLOv10 when processing complex PCB features, we introduce the Multiscale Edge Strengthening (MSES) structure to replace the traditional C2F module. The MSES structure employs a multi-branch design for multidimensional learning of minor PCB features enhanced by edge information. During inference, it is simplified to a single branch to retain high-frequency information and reduce memory consumption. Secondly, in the neck of the network, we incorporate the Improved SPDConv module to minimize the loss of fine-grained information and enable multiscale feature extraction for PCB defect images. Lastly, we optimize the network structure using the Layer Adaptive Magnitude-based Pruning (LAMP) method and design a dual-distillation strategy to further refine the improved YOLOv10 algorithm. This strategy leverages two distinct network heads for knowledge transfer, enhancing the learning effectiveness of the student model and improving accuracy while reducing model size. Experimental results demonstrate that the proposed MS-YOLO outperforms several state-of-the-art models, achieving a mean Average Precision (mAP@50) of 98. 9%. This validates the significant improvements of MS-YOLO in detection accuracy, operational efficiency, and practical applicability.
Chen et al. (2025) studied this question.