An Enhanced Method for Swept‐Threshold Sampler for IR‐UWB Applications

This paper presents a method for swept‐threshold ADCs used in IR‐UWB applications. In conventional designs, the threshold voltage sweeps the full‐scale range to perform exact comparisons. The proposed approach divides the full‐scale voltage into two halves by initially comparing the input signal with half of the full‐scale voltage ( V FS /2). Based on this comparison, the threshold voltage is swept only within one‐half of the range, effectively detecting the most significant bit (MSB). This technique results in a reduction of one bit in the DAC and counter resolution, halving the capacitor size and the time required to reach the final output code. Consequently, power consumption and chip area are significantly reduced. Additionally, the shorter conversion time enables improved signal‐to‐noise ratio (SNR) through time averaging. The circuit was designed and simulated using the TSMC 65 nm CMOS process with a supply voltage of 1.2 V. Post‐layout simulation results demonstrate that the proposed 6‐bit converter achieves a sampling rate of 16.66 GS/s with a total power consumption of 27.33 mW, representing a 15% reduction compared to conventional methods. The chip area is approximately 0.149 mm 2 , reduced by 18.58%, and the maximum integral nonlinearity (INL) is measured at 0.55, demonstrating the effectiveness of the proposed architecture.