A lightweight computation architecture with current-mode MAC unit for classification applications

Convolutional neural networks (CNNs) are increasingly being deployed on edge devices, where stringent power and latency constraints require highly efficient hardware implementations. This paper introduces an energy-efficient analog computing architecture designed for binary classification, with an emphasis on system-level integration and algorithm-hardware co-design. The system integrates a current-mode active pixel sensor (APS) with analog computing units—multiply-accumulate (MAC), ReLU, and max pooling—into a continuous analog-domain processing pipeline. This integrated approach minimizes data conversion, requiring only a single analog-to-digital conversion for the final classification result, thereby significantly improving energy efficiency. Furthermore, a comprehensive analysis of hardware nonidealities is conducted from multiple perspectives, and an algorithm-hardware co-design method is proposed to mitigate degradation in inference accuracy. The prototype chip, fabricated in a 55 nm CMOS process, consumes only 191.5 μW and delivers 3 TOPS/W. Supported by the co-design method, it achieves an accuracy of 97.2% on the LFW dataset. This work demonstrates a practical, fully integrated analog solution for low-power binary classification in intelligent sensing systems.