Novel algorithm improves latency and reduces power consumption in pipelined ADCs, suggesting enhanced hardware efficiency.
Pipelined analogue‐to‐digital converters suffer from inter‐stage gain errors and inter‐stage nonlinearity errors due to gain variations and nonlinearity in residue amplifiers. While a polynomial‐based calibration algorithm can address these errors, its conventional implementation demands excessive hardware resources and power consumption. This letter introduces a novel calibration algorithm that combines precomputation with a lookup table, achieving improved hardware efficiency while maintaining calibration accuracy and reducing latency.
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Yu et al. (2025) studied this question.
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