High-Throughput and Memory-Efficient Pipeline Key–Value Store Architecture on FPGA

The increasing speed of network connections is placing increasing demands on the performance of network security and monitoring systems, where Key–Value Stores (KVSs) are becoming critical in network security applications. There is a compelling demand to enhance both the throughput and storage utilization of KVSs. The FPGA-based parallel architecture presents a remarkable opportunity to achieve outstanding performance and power efficiency. In this paper, we propose an FPGA-based implementation of KVSs using a multi-level multi-hash approach, which can effectively avoid false misses and false inserts, in addition to addressing skewed workloads. Decoupled storage exceeds 95% memory utilization, and the pipeline scheme achieves high performance, reaching 400 million requests per second (MRPS). The latency of insert, query, and delete operations is only 60 ns.