Workload-Dependent Vulnerability of SDRAM Multi-Bit Upsets in a LEON3 Soft-Core Processor

Multi-bit upsets (MBUs) are a growing reliability threat in high-density SDRAM, particularly in radiation-prone embedded systems. This paper presents a large-scale FPGA-based fault injection (FI) study targeting external SDRAM in a cache-enabled LEON3 SPARC V8 processor, with over 300,000 dual-bit MBUs injected across three diverse workloads: Fast Fourier transform (FFT), matrix multiplication (MulMatrix), and advanced encryption standard (AES). Our results reveal a profound dependence of MBU manifestation on application semantics: memory-intensive benchmarks (FFT, MulMatrix) exhibit high fault detectability through data store and access exceptions, while the AES workload demonstrates exceptional intrinsic masking, with the vast majority of MBUs producing no observable effect. These results demonstrate that processor vulnerability to MBUs is not uniform but fundamentally shaped by workload characteristics, including memory access patterns, control flow regularity, and algorithmic redundancy. The study provides a hardware-validated foundation for designing workload-aware fault tolerance strategies in space-grade and safety-critical embedded platforms.