Silicon carbide (SiC) MOSFETs, as one of the representative power electronic devices, have faced reliability challenges due to threshold voltage (Vth) instability under dynamic gate stress. To explore the underlying mechanisms, this work investigates 4H-SiC MOS structures (P-MOS and N-MOS) under AC bias temperature instability (AC BTI) stress, utilizing a laser to generate minority carriers and simulate realistic switching conditions. Through combined capacitance–voltage (C-V) and gate current–voltage (Jg-Vg) characterizations on P-MOS and N-MOS devices before and after degradation at different temperatures, we reveal a critical temperature dependence in defect interactions. At room temperature, degradation is dominated by electron trapping in shallow interface states and near-interface traps (NITs). In contrast, high-temperature stress activates charge exchange with deep-level, slow states. Notably, a positive VFB shift is consistently observed in both N-MOS and P-MOS devices under AC stress, confirming that electron trapping is the dominant cause of the commonly observed positive Vth shift in SiC MOSFETs. These findings clarify the distinct defect-mediated mechanisms governing dynamic Vth instability in SiC devices, providing fundamental insights for interface engineering and reliability assessment.
Yu et al. (Mon,) studied this question.