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February 5, 2026Advanced ScienceOpen Access

Dual‐Modulated Vertically Stacked Transistors With Fully Laminated Plate‐Type Architecture Featuring Nanoscale Channel Length

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Authors

GPGoeun PyoSHSu Jin HeoJJJeonggyun Jang

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Overview

Innovative design enhances performance and stability in nanoscale transistors, indicating promise for efficient low-power electronics.

Key Points

  • The goal is to improve the performance and stability of nanoscale transistors using a new design approach.
  • Introduced a laminated plate‐type architecture with dual-gate control.
  • Employed a micro‐hole patterned electrode for effective gate field penetration.
  • Utilized a graphene electrode for Fermi-level modulation.
  • Implemented a leakage blocking layer to reduce unwanted carrier injection.
  • Achieved low off‐state current of approximately 10−12 A.
  • Reported an on/off current ratio exceeding 10^6 at 3 V.
  • Delivered high output currents: 1 mA cm−2 at 0.1 V and 50 mA cm−2 at 1 V.
  • Maintained near-zero threshold voltage despite nanoscale channel length.

Cite This Study

Pyo et al. (2026) studied this question.

synapsesocial.com/papers/698435c9f1d9ada3c1fb4ef2https://doi.org/10.1002/advs.202519410
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