A Power Amplifier With Darlington Cell in 0.18‐μm CMOS Technology

A power amplifier (PA) with Darlington cell in 0.18‐μm CMOS technology is reported in this letter. By adopting the Darlington cell with cascode structure, the proposed CMOS PA improves the performance. The proposed CMOS PA owns the two‐stage cascade topologies formed by the common source (CS) and common gate (CG) cascode configurations. For the proposed CMOS PA, the first stage is the Darlington cascode topology, and the second stage is the cascode topology, respectively. The proposed CMOS PA at 3.5 GHz has the measured power gain of 18.13 dB, the measured saturated power ( P sat ) of 5.16 dBm, and the measured power added efficiency (PAE) of 8.25%, respectively. The proposed CMOS PA supplied by a 1.8‐V supply dissipates 40.5 mW.