Investigation of Ohmic Contacts and Resistances of a 4H-SiC CMOS Technology up to 550°C

In this work, the temperature dependence of all relevant resistances of a 4H-SiC CMOS technology for high temperature applications is investigated from room temperature up to 550 °C. This includes sheet resistances (Rsh) of differently doped regions, metallization layers (Ti/Pt and Ti/Pt/Ti layer stacks), and highly n-doped polycrystalline silicon as well as specific contact resistances (ρc) to highly n- and p-doped 4H-SiC obtained by N and Al implantation, respectively. Different test structures were used for comparison and consistency of the results. Positive temperature coefficients of resistance were observed for the metallization layers (2700 ppm/K) and for highly n-doped polycrystalline silicon (1360 ppm/K). Rsh and ρc for highly n-doped 4H-SiC regions show only moderate variation with temperature whereas a rather strong decrease of Rsh and ρc can be observed for highly p-doped 4H-SiC and of Rsh for moderately p-doped 4H-SiC from room temperature up to 200 °C which is mainly due to incomplete ionization of Al-doped regions. For implanted regions, modelled Rsh(T) data qualitatively confirm measured results.