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February 12, 2026ACM Transactions on Design Automation of Electronic Systems

DyLDPC: A Dynamic LDPC Code with Variable Correction Capability to Improve Decoding Performance for 3D NAND Flash Memory

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Authors

GRGeyang RenMZMeng ZhangYLYangyi Li

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Overview

Demonstrates improved decoding performance in 3D NAND flash memory, suggesting enhanced data reliability with dynamic error correction.

Key Points

  • To improve data reliability in 3D NAND flash memory by optimizing error correction capabilities dynamically based on varying error rates.
  • Proposed DyLDPC code adjusts error correction dynamically based on raw bit error rate (RBER) variations.
  • Evaluated correction performance under different retention times and program/erase cycles.
  • Implemented differentiated LDPC codes for significant and least significant bit pages in MLC NAND.
  • DyLDPC reduces decoding iterations by 8.1% compared to static error correction schemes.
  • Achieved an average latency reduction of 74% with DyLDPC.
  • LSB decoding latency decreases by 27.8% with differentiated LDPC codes.

Cite This Study

Ren et al. (2026) studied this question.

synapsesocial.com/papers/698d6de45be6419ac0d53180https://doi.org/10.1145/3796534
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