This paper presents a highly energy-efficient adiabatic capacitive neuron (ACN) hardware implementation of an artificial neuron (AN), with improved energy efficiency, robustness, and scalability over previous work. A single-neuron ACN with 12 one-bit capacitive synapses is implemented in 0.18 μm CMOS technology, supporting both positive and negative synaptic weights. A novel threshold logic (TL) circuit is introduced to realize the binary AN activation function, explicitly designed to minimize input-referred offset and ensure robust decision making under dynamic adiabatic operation. The TL performance is evaluated across three process corners and five temperatures ranging from –55 °C to 125 °C. Post-layout simulations show that the proposed TL achieves a maximum rising and falling offset voltage of 9 mV, compared to 27 mV (rising) and 5 mV (falling) for a conventional TL implementation across process and temperature variations. The proposed ACN achieves over 90% total synapse energy savings (over 12× improvement) relative to an equivalent non-adiabatic CMOS capacitive neuron (CCN) over operating frequencies from 500 kHz to 100 MHz. A 1000-sample Monte Carlo analysis incorporating process variation and mismatch confirms consistent energy savings exceeding 90% in the synapse energy profile. Supply voltage scaling further demonstrates sustained energy savings above 90%, except for the all-zero input condition, without loss of functionality. These results demonstrate that adiabatic charge recovery, combined with a robust low-offset threshold logic design, enables substantial energy reduction while maintaining reliable neuron operation across wide operating conditions.
Maheshwari et al. (2026) studied this question.