PulseExploreJournal ClubDebatesTrendingResearchersJournals
Instagram
HomeExploreJournal ClubTrending
Synapse
⌘+K
Synapse
March 3, 2026SHILAP Revista de lepidopterología0 citationsOpen Access

An Efficient-Energy Charge-Domain Convolution Operator for CNN

View Full Paper
JDJose-Angel Diaz-MadridGDGines Domenech-AsensiRRRamon Ruiz-Merino

Key Points

  • The convolution operator processes a 32×32 grayscale pixel image in just 5.12μs, demonstrating remarkable speed.
  • Achieving an efficiency rate of 22154 1b-TOPS/W, the operator utilizes only 117 μW of power during operation.
  • The approach integrates a voltage divider and selector circuits to manage multiplications with multibit weights effectively.
  • Implemented using 180 nm CMOS technology, the efficiency closely aligns with ideal processing, reaching up to 99% similarity.

Abstract

This paper proposes a compact and low-power mixed-signal approach for implementing a convolutional operator in the charge domain. The circuit integrates a voltage divider with selector circuits to perform multiplications using multibit weights ranging from -1 to +1 and analog signals. Additionally, charge-domain average circuits accumulate, sum, and average these multiplications sequentially. For this study, a new convolution operator was designed to compute the convolution product over a pixel using a multibit 3x3 mask. Subsequently, a computing circuit was developed to perform 30 convolution operations in parallel per clock cycle. The charge-domain average circuit was synthesized in 180 nm CMOS technology, and post layout simulation results indicate its capability to convolve a 32×32 grayscale pixel image in 5.12μs while consuming only 117 μW, achieving an efficiency of 22154 1b-TOPS/W (1-bit tera-operations per second per watt) with a similarity to ideal processing of up to 99%.

Ask AI
Helpful
Bookmark
Share
View Full Paper

Cite This Study

Diaz-Madrid et al. (2026) studied this question.

synapsesocial.com/papers/69a75b21c6e9836116a21e0chttps://doi.org/10.1109/access.2026.3657997
Ask AI
Helpful
Bookmark
Share
View Full Paper

Also Consider

Synapse has enriched 5 closely related papers on similar clinical questions. Consider them for comparative context:

  1. 1A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs2023 · 121 citations
  2. 2A 128x128 SRAM Macro with Embedded Matrix-Vector Multiplication Exploiting Passive Gain via MOS Capacitor for Machine Learning Application2021 · 6 citations
  3. 3IMAC: In-Memory Multi-Bit Multiplication and ACcumulation in 6T SRAM Array2020 · 129 citations
  4. 4A PVT Robust 8-Bit Signed Analog Compute-In-Memory Accelerator with Integrated Activation Functions for AI Applications2024 · 6 citations
  5. 5A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro2023 · 23 citations