This paper proposes a compact and low-power mixed-signal approach for implementing a convolutional operator in the charge domain. The circuit integrates a voltage divider with selector circuits to perform multiplications using multibit weights ranging from -1 to +1 and analog signals. Additionally, charge-domain average circuits accumulate, sum, and average these multiplications sequentially. For this study, a new convolution operator was designed to compute the convolution product over a pixel using a multibit 3x3 mask. Subsequently, a computing circuit was developed to perform 30 convolution operations in parallel per clock cycle. The charge-domain average circuit was synthesized in 180 nm CMOS technology, and post layout simulation results indicate its capability to convolve a 32×32 grayscale pixel image in 5.12μs while consuming only 117 μW, achieving an efficiency of 22154 1b-TOPS/W (1-bit tera-operations per second per watt) with a similarity to ideal processing of up to 99%.
Diaz-Madrid et al. (2026) studied this question.
Synapse has enriched 5 closely related papers on similar clinical questions. Consider them for comparative context: