Making Root Cause Localization on FPGA Simulation Tools Robust

Field Programmable Gate Array (FPGA) simulation tools have become indispensable in the design, simulation, and verification of Register Transfer Level (RTL) designs, serving as critical instruments in modern digital system development. As the complexity and scale of FPGA simulation tools continue to expand, the bugs root causes have become increasingly diverse, which leads to challenges in constructing comprehensive multi-dimensional bug features and locating test cases that trigger the root causes. In response to these challenges, we propose RCLoc, an innovative bug root cause localization framework for FPGA logic synthesis tools. RCLoc enhances diagnostic accuracy by leveraging a detailed analysis of multi-dimensional bug features extracted from test cases, as well as addressing feature extraction biases caused by redundant test cases. Specifically, RCLoc comprises two components: the Test-case Confidence Computation component and the Test-case Redundancy Elimination component. The TCC component integrates bug-related features, such as code coverage, code mutation, text complexity, and similarity, along with suspiciousness metrics, to generate a robust confidence matrix, i.e., the bug correlation matrix, that quantitatively evaluates the relevance of each test case to the underlying bug root causes. The TRE component uses this bug correlation matrix to systematically assess the contribution of individual test cases, identify redundant or non-informative cases, and subsequently eliminate them, thereby removing the noise and bias that redundant test cases may inadvertently introduce during the feature extraction process. Extensive experimental evaluations were carried out on 141 bugs obtained from two prominent open-source FPGA simulation tools, namely Iverilog and Verilator. The results demonstrate that RCLoc significantly outperforms state-of-the-art techniques, achieving improvements of 26.0% in Mean First Rank (MFR) and 30.3% in Mean Analysis Rank (MAR). On average, RCLoc reduces the fault localization cost by nearly 26% and 30% for FPGA engineers, highlighting its potential to substantially improve the efficiency and accuracy of bug diagnosis in complex FPGA simulation environments.