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This research aims to investigate the instruction-level performance limiting mechanisms of Tensor Cores in NVIDIA CMP 170HX.

March 15, 2026Open Access

Microbenchmarking Instruction-Level Tensor Core Throttling in NVIDIA CMP 170HX

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This research aims to investigate the instruction-level performance limiting mechanisms of Tensor Cores in NVIDIA CMP 170HX.
Microbenchmarking methods were employed to systematically analyze instruction execution.
Controlled experiments examined ILP scaling, warp scaling, dependency chains, and cross-pipeline interference.
A fixed-cycle instruction execution throttling of 256 cycles was revealed for the CMP 170HX's Tensor Cores.
Only 4 warps per SM can issue Tensor Core instructions simultaneously, limiting FP16 power to 1/32 of the theoretical peak.
A theoretical model was constructed linking microarchitecture to total computing power of 6.3 TFLOPS.

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Microbenchmarking unveils instruction-level throttling in NVIDIA CMP 170HX Tensor Cores, indicating limited computing power.

Kangwei Xing (2023) studied this question.

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