Generic logic block based on bias-gated 2D MoS2 transistors

Integrating two-dimensional (2D) semiconductors and CMOS technology is a promising pathway for next-generation integrated circuits. However, the implementation of this strategy is hindered by the limited polarity modulation of 2D semiconductors and the inherent characteristics of CMOS architectures. Here, we report a generic logic block (GLB) that uses bias-gated molybdenum disulfide transistors (BG-FET). The BG-FETs exhibit threshold-adaptive field-effect characteristics through simple bias manipulation, enabling good rail-to-rail operation in the inverter circuits. The GLB composed of four BG-FETs can perform reconfigurable logic operations in a single circuit, including basic gate circuits, half-adder, multiplexer, encoder and static-random-access-memory. In contrast, conventional CMOS circuits require at least 100 transistors to perform the same set of operations. We further integrate flip-flop circuits and arithmetic logic units by cascading as-fabricated GLBs, featuring a transistor count saving of over 60% compared to CMOS design. Collectively, BG-FET-based GLB emerges as a post-CMOS integration technology with compelling potential. 2D semiconductors are considered a promising platform to complement silicon in next-generation electronics. Here, the authors report the fabrication of generic logic blocks based on bias-gated 2D MoS2 transistors, showing the design of logic circuits with transistor count saving of over 60% compared to conventional Si electronics.