DeVSA: A Density-Efficient Vector SNN Accelerator Exploiting Compressor-TreeReuse for Spike-Weight Accumulation

Spiking neural networks are promising for energy-efficient edge intelligence, but mapping 1-bit spikes onto high-precision vector datapaths leads to underutilization and low compute density. This paper presents DeVSA, a 16-lane vector SNN accelerator for LIF-based SNNs with 1-bit spikes and BF16 weights. DeVSA reuses the compressor tree of a standard BF16 multiplier to support an 8-way spike-weight dot-product (DOT8) by directly reducing exponent-aligned, spike-gated mantissas without introducing a dedicated SNN accumulation datapath, preserving full BF16 multiplication capability. DeVSA integrates single-cycle fire-and-reset to streamline per-timestep LIF updates. A hardware micro-loop controller amortizes instruction fetch/decode over up to 256 iterations, and a shared reconfigurable adder tree supports both element-wise operations and hierarchical reductions. Synthesized in 28-nm CMOS, DeVSA operates at 1.4 GHz and achieves a peak throughput of 340.6 GFLOPS at 163 mW, corresponding to 2.09 TFLOPS/W and 838 GFLOPS/mm2 post-synthesis compute density in DOT8 mode. On N-MNIST, DVS-Gesture, and CIFAR-10, DeVSA provides end-to-end effective speedups of up to 7.76× over standard vector baselines and outperforms state-of-the-art programmable SNN processors by 5.0×–7.9× in estimated post-P&R density under 50% utilization. DeVSA shows that compressor-tree reuse can deliver high compute density and energy efficiency with vector-level programmability for SNN inference.