Phase Margin Circuit Design Based on Cascaded DC-DC Converter and Two-Stage Op-Amp with Cascode Compensation

This paper proposes a Cascode phase compensation network structure for controlling Buck–Boost converters to achieve wide-bandwidth and high-speed operation. The proposed scheme relocates the compensation capacitor (CC) from the traditional position “across the first-stage output and the second-stage output” to a new position “between the source of the first-stage Cascode common-gate transistor and the second-stage output.” By integrating their high common-mode rejection ratio and power supply rejection ratio, a global system loop with robust interference immunity is constructed. The results indicate that a dominant-pole frequency of 10 kHz is achieved with our proposed structure compared to the circuit without Cascode compensation, representing a tenfold increase. As a result, a phase margin (PM) of up to 58.36° is achieved, which is improved by 9.1%. This work can provide an effective reference for achieving stable and rapidly responsive power conversion.