Unveiling the Roles of Bulk and Interface Defects of a High-K Dielectric TiO2-Based Charge-Trapping Layer in the Device Failure of Non-Volatile Charge-Trapping Memory

Charge-trapping memory (CTM) exhibits significant potential in high-density memory, yet reliability degradation resulting from the coupling of program/erase (P/E) cycles and electrical stress remains a key bottleneck for large-scale commercialization. This study focuses on a Au/Al2O3/TiO2/p-Si CTM device, systematically investigating the device failure mechanism under continuously operating P/E cycles and constant voltage stress (CVS), with emphasis on elucidating the synergistic effect of bulk and interface defects on performance decay. Mechanistically, oxygen vacancies in TiO2 serve as defect precursors, which form Frenkel pairs under electric field stress and further promote the formation of new defect precursors, thereby driving a self-sustaining defect evolution process. Interface traps, by contrast, arise from the cleavage of interfacial Si-H bonds triggered by electric field stress, resulting in a net elevation of the interface state density. The passive effects from the bulk and interface defects may give rise to issues, such as threshold voltage drift and decreased P/E speed. This work provides in-depth insights into the device failure mechanism of CTM, offering critical theoretical support for optimizing fabrication processes and enhancing long-term reliability.