Energy-Dissipating Integration Circuit for High-Impedance Solid-State Fault Current Limiters to Improve Interruption Speed in HVDC Systems

• Expansion and development of MT-HVDC systems increases the DC fault current levels. • The application of DC FCLs provides an effective approach to reduce the DCCB requirements. • This paper proposes a modified high-impedance solid-state FCL to be used in MT-HVDC systems. • It significantly reduces the dissipated energy of DCCB arresters and the interruption time of DCCB. • The PSCAD/EMTDC software is used in this study. Expansion and development of high voltage direct current (HVDC) systems increases the DC fault current levels. The application of DC fault current limiters (FCLs) offers an effective solution to mitigate the breaking burden and the interruption requirements of DC Circuit Breakers (DCCBs) by limiting DC fault currents in HVDC systems. This paper introduces a novel modified high-impedance solid-state FCL (MHI-SSFCL) topology to be used in HVDC systems. The key novelty of the proposed MHI-SSFCL is an energy-dissipating circuit strategically placed in parallel with the coupling inductors. This integrated path provides a dedicated freewheeling path to dissipate the magnetic energy stored in the inductors. This core innovation yields two main contributions: (1) Significant reduction in the energy dissipation required from the DCCB Metal-Oxide Arrester (MOA), and (2) reduction the breaking speed, thereby reducing the interruption requirements for the DCCB. The operational principles and parameter design of the MHI-SSFCL are analytically presented. Simulation results in a three-terminal HVDC system, modeled in PSCAD/EMTDC, demonstrate that the proposed FCL significantly outperforms the conventional HI-SSFCL, reducing the MOA energy dissipation and the required breaking time. Also, these performance advantages are validated through experimental results from a scaled laboratory prototype.