The number of IPv4 routing table entries was around 460k in 2012 and is growing at a rate of 10% per year. The continuing increase of network-connected devices risks depletion of IPv4 addresses. As for IPv6, the number of routing-table entries is about to reach 16k with a rapid annual growth rate of 90%. This growth trend will continue in the Internet-of-Things era. In growing network applications with large amounts of traffic, there is a demand for routers and switches capable of packet processing for applications such as forwarding, quality of service, classification and access control. Fully parallel ternary content-addressable memories (TCAMs) are the key devices to handle the large number of routes in the lookup table with high-throughput low-latency header processing [1-6]. Realizing both high-density (high-capacity) and high-speed search operation is a challenge due to high power consumption and diminishing signal integrity for search operations. Process scaling is important to achieve a high-density high-performance TCAM, but it incurs the decrease of operating margin caused by threshold-voltage variation. This paper presents a 400MHz 4-paralleled search-operation 80Mb TCAM test-chip in a 28nm process that can accommodate 1M entries. This chip has three key features: flexible search mode, row and column shift redundancy, and search omission with valid-bit. With flexible search mode, the TCAM can be adapted to both IPv4 and IPv6.
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Nii et al. (2014) studied this question.
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