This paper presents a four-phase buck converter with capacitor-current-sensor (CCS) calibration for load-transient-response optimization that targets the theoretically minimal output-voltage undershoot ΔV US , overshoot ΔV OS , and settling time t S when large and rapid load-current transients ΔI load occur. The proposed CCS calibration calibrates the CCS' equivalent impedance to emulate a scaled replica of the output capacitor's impedance Z Co . Thus, the CCS can accurately sense the output-capacitor current I Co despite Z Co variations due to different output voltages, fabrication variations, and printed-circuit-board parasitics. Moreover, a load-transient optimizer is proposed to utilize the accurately sensed I Co to instantly detect the large and rapid ΔI load , and synchronously control the charging and discharging durations of the output inductors in all four phases, resulting in small ΔV US /ΔV OS and short t S . The converter is implemented in a 0.18-μm CMOS process with 1.93-mm 2 chip area. For a 1.8-A/5-ns step-up (step-down) ΔI load , the measured ΔV US (AV OS ) and t S are 92 mV (75 mV) and 133 ns (110 ns), respectively. Compared with other state-of-the-arts, both the measured ΔV US (ΔV OS ) and t S in this paper are the closest to their respective theoretical limits, i.e., the fastest load-transient response with the smallest ΔV US (ΔV OS ) and the shortest t S under the same input voltage, output voltage, output inductance, and output capacitance.
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Huang et al. (2017) studied this question.
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