A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC

This article demonstrates the potential of deep-subthreshold mixed-signal circuits in delivering medium-to-high performance to supply-constrained, energy-harvesting Internet of Things (IoT) sensing applications. This effort encapsulates the design and implementation of an ultra-low-voltage (ULV) 0. 2-V open-loop VCO-based analog-to-digital converter (ADC). A replica VCO facilitates variation-aware VCO analog linearization. Analog phase-domain signal processing (APSP) techniques for beat-frequency extraction, phase-interpolation, and phase-folding relax constraints on both voltage-to-frequency analog circuitry and frequency-to-digital synchronous digital hardware. High-speed multi-phase frequency-to-digital converters (FDCs) and multi-rate digital back-end enable a sampling speed of 35 MS/s. The ADC prototype is implemented in 28-nm CMOS and achieves a peak SNDR of 64. 4/59. 9 dB, equivalent to an ENOB of 10. 4/9. 7 over 80-/160-kHz bandwidth (BW). The ADC core occupies an active area of 0. 12 mm 2 and consumes 15. 9 W, resulting in a Walden and Schreier FoM of, respectively, 73. 3/61. 5 fJ/c-s and 161. 4/159. 9 dB at the corresponding BW configurations. Measurements across multiple ICs and supply voltages consolidate the value of variation-aware deep-subthreshold open-loop ADCs.