2 MB Array-Level Demonstration of STT-MRAM Process and Performance Towards L4 Cache Applications

In this paper, we discuss array-level MTJ process, performance, and reliability requirements for STT-MRAM operation in an L4 Cache application. We demonstrate 2 MB arrays of scaled-size MTJ devices capable of meeting L4 Cache specifications across all proposed temperatures of operation. The technology achieves ECC-correctable bit fail rates for a 20 ns write time, a 4 ns read time, endurance of 10 12 cycles, and retention of 1 second at 110 C. Key to achieving these results is the careful co-optimization of the MTJ stack and etch process to minimize array-level tail failure events.