This paper presents a solid-state circuit breaker (SSCB) designed to reduce the conduction loss while enabling a compact implementation. Compared with mechanical circuit breakers, SSCBs offer faster cutoff speeds and superior repetitive operation. However, the electrical characteristics of power semiconductor devices are strongly affected by junction temperature rise, which leads to increased on-resistance, reduced conduction efficiency, and diminished compactness. To address these issues, the impacts of device parallelization and junction temperature on conduction loss were investigated through static characteristic measurements of an SiC FET device. Furthermore, implementation and design methods for realizing an SSCB using this device are discussed, highlighting, the practical implementation constraints and design trade-offs of SSCBs. Experimental validation in a 400V, 100A DC distribution system demonstrated that the proposed SSCB implemented in two layout configurations achieves a conduction efficiency of up to 99.94%, comparable to that of mechanical circuit breakers, while enabling an efficient and compact implementation for low-voltage DC applications.
Takamori et al. (Thu,) studied this question.