Through-silicon vias (TSVs) are critical vertical interconnects in three-dimensional integrated circuits (3D ICs). The Bosch Deep Reactive Ion Etching (DRIE) process creates periodic scallops on the sidewall, known as line edge roughness (LER), which affects device performance and reliability. However, existing methods can only characterize TSV sidewall qualitatively or require destructive sample preparation, making model-based quantitative LER characterization unavailable for high-aspect-ratio TSVs. This study presents a shadowgraphy-based method to address this gap. Using oblique-angle infrared (IR) illumination, the system projects both top and bottom contours onto a single imaging plane, enabling extraction of critical dimensions (CD) including two diameters and depth. Combined with physical modeling, this approach also proposes a model-based framework for sidewall LER estimation. Monte Carlo Ray Tracing (MCRT) simulations established and verified the correlation between scattering and edge blur. Since inverting this relationship analytically is intractable, Random Forest (RF) and Convolutional Neural Network (CNN) models were employed to estimate roughness from shadow edge profiles. Validation on simulated data achieved root mean square error (RMSE) of approximately 0.03 μm over the 0.01 to 0.20 μm range. Geometric validation demonstrated an RMSE of 0.19 μm for top diameter and 1.04 μm for depth compared to optical microscopy (OM) and scanning electron microscopy (SEM) references. The trained models were applied to experimental shadow images for non-destructive LER estimation as a process monitoring metric. This study shows the potential for TSV and through-glass via (TGV) CD metrology, offering a practical solution for inline metrology in advanced semiconductor packaging.
Lu et al. (Thu,) studied this question.