Robust Voltage Stability Enhancement of DFIG Systems Using Deadbeat-Controlled STATCOM and ADRC-Based Supercapacitor Support

The increasing penetration of Doubly Fed Induction Generator (DFIG)-based wind energy systems raises major concerns regarding voltage stability and Fault Ride-Through (FRT) capability under grid disturbances and wind speed variations. This paper proposes a coordinated control framework for a grid-connected DFIG system, where a Static Synchronous Compensator (STATCOM) based on discrete-time deadbeat current control is integrated with a Supercapacitor Energy Storage System (SCES) connected to the DC link through a bidirectional DC-DC converter governed by cascaded Active Disturbance Rejection Control (ADRC). The deadbeat-controlled STATCOM provides fast reactive current injection for voltage support during sag and swell events, while the cascaded ADRC enhances DC-link voltage regulation and suppresses rotor-speed oscillations. Comprehensive MATLAB/Simulink simulations are carried out under variable wind speed and severe grid disturbances up to 80% voltage sag and 50% voltage swell. For voltage regulation, the proposed method is compared with SVC and PI-based STATCOM. In addition, SCES control performance is evaluated by comparing PI, single ADRC, and cascaded ADRC in terms of DC-link voltage overshoot, undershoot, and ripple. The results show clear improvements in voltage response and transient performance. Under a 20% voltage sag, the proposed deadbeat-controlled STATCOM significantly improves the dynamic response, where the undershoot is reduced from 0.125 p.u. (with SVC) to 0.04 p.u., and the settling time is shortened from 0.04 s to 0.025 s. Under a severe 80% sag, the overshoot is limited to 0.02 p.u., compared with 0.13 p.u. for the SVC and 0.15 p.u. for the PI-based STATCOM. Similarly, under a 50% voltage swell, the overshoot is reduced to 0.20 p.u., compared with 0.46 p.u. for the SVC and 0.27 p.u. for the PI-based STATCOM. Regarding the DC-link performance under 80% sag, the proposed cascaded ADRC-based SCES limits the overshoot and undershoot to 6 V and 2 V, respectively, compared with 39 V and 32 V for the PI-based SCES. These results confirm the superior damping, disturbance rejection, and FRT enhancement achieved by the proposed strategy.