We demonstrate the improvement of memory window (MW) and endurance by controlling the interfacial trap charges in Si-channel HfO-FeFET based on the accurate understanding of interaction between the polarization and the trap charges by means of fast current measurement. By introducing metal traps into the channel-side interfacial layer (IL), not only the IL degradation during cycling is suppressed, but also the ferroelectric phase of HfO on the IL is stabilized, which is confirmed by crystallinity analysis after cycling. In addition, the charge-control operation sequence is employed, leading to the largest MW (> 2 V) at 10 7 cycles ever reported. Trap-controlled IL is also applied to 3D (vertical) FeFET.
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Suzuki et al. (2023) studied this question.