Design and Evaluation of an FPGA-based Hardware Accelerator for Deflate Data Decompression

Data compression is an important technique for coping with the rapidly increasing volumes of data being transmitted over the Internet. The Deflate lossless data compression standard is used in several popular compressed file formats including the PNG image format and the ZIP and GZIP file formats. Consequently, several implementations of hardware accelerators for Deflate have been proposed. The recent availability of distributed field-programmable gate arrays (FPGAs) in the Internet cloud and the growing demand for decompressing compressed data that is streamed from remote servers make FPGA-based decompression accelerators commercially attractive. This paper describes an efficient implementation of the Deflate decompression algorithm using high-level synthesis from designs, specified in C++, down to optimized implementations for a Xilinx Virtex UltraScale+ class FPGA. When decompressing the Calgary corpus benchmark, our decompressor has average input (output) data throughputs of 70.7 (246.4) and 130.6 (386.6) MB/s for dynamically and statically encoded files, respectively. This performance is comparable to the 375 MB/s output throughput of Xilinx's state-of-the-art proprietary Deflate decompressor design.