29.7 A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS

Single-inductor multiple-output (SIMO) converters present a promising technology for enabling fine-grained supply-voltage (V dd ) domains in SoCs. With efficiencies approaching those of buck converters, SIMO converters allow multiple domains to share a single inductor, thus reducing the use of bulky passive components [1-5]. However, SIMO converters suffer from a poor transient response and significant ripple, requiring extensive V dd margining. Operation at an elevated V dd -and, therefore, the load-current (I load )-inflates power draw and further reduces system efficiency (η system ), i.e. the ratio of the useful (margin-free) output power to input power draw.