As transistor scaling approaches physical limits, the accurate quantification of thermal conductivity and interfacial thermal conductance for semiconductor materials within chips has emerged as a critical bottleneck for next-generation integrated-circuit design and thermal management. Existing thermal measurement techniques are challenged by devices exhibiting concurrent high thermal conductivity, multilayer structures, and pronounced anisotropy, often requiring complex procedures, prolonged measurement times, and multi-method integration—yet still yielding unsatisfactory accuracy. To overcome these limitations, we propose a time-domain electrical heating (TDEH) method that enables simultaneous high-resolution characterization of out-of-plane and in-plane thermal conductivity as well as heat capacity. The TDEH method was validated across a broad thermal conductivity range (1–4000 W/(m K)), showing excellent agreement between the measured thermal conductivity, heat capacity, and other standard references. Furthermore, the successful application of TDEH to both strongly anisotropic low-thermal-conductivity Ga2O3 thin films and polycrystalline diamond demonstrates its versatility for comprehensive thermal characterization of semiconductor materials. Our work provides a versatile, high-precision, and easily implementable solution for chip's thermal characterization, offering an essential tool for thermal management design in high-power and highly integrated chips.
Zhao et al. (2026) studied this question.