Design and Performance Analysis of MultiDigit BCD Adder Using BrentKung Architecture

The design of high-speed and power-efficient arithmetic units is a critical requirement in modern VLSI systems, particularly for applications that demand accurate decimal computations such as financial processing and digital signal processing.This work presents an optimized multi-digit Binary Coded Decimal (BCD) adder based on a parallel prefix structure using the Brent-Kung Adder (BKA), and compares its performance with a conventional Carry Lookahead Adder (CLA) based design.The proposed and existing architectures are implemented for multiple digit configurations and evaluated in terms of delay and power consumption.The results indicate that the proposed BKA-based BCD adder achieves a significant reduction in delay of approximately 32% for lower digit designs and about 22% for higher digit designs.Similarly, power consumption is reduced by around 7% for smaller configurations and up to 10% for larger configurations when compared to the conventional CLA-based approach.These improvements are attributed to the reduced logic depth and efficient carry propagation mechanism of the Brent-Kung architecture.Furthermore, the proposed design demonstrates better scalability with increasing digit size, making it highly suitable for high-performance and low-power VLSI applications.