Heat Dissipation Improvement Using Plugged Sidewall for Three-dimensional (3D) Package of High-stacked High Bandwidth Memory (HBM)

Three-dimensional (3D) High Bandwidth Memory (HBM) packages suffer from limited heat removal through the low thermal conductivity epoxy molding compound (EMC). Heat from the logic die is forced to traverse only through the stacked DRAM dies, which elevates the logic die temperature and corner stress. We propose a hollow rectangular copper structure named a plugged sidewall, embedded in the mold region surrounding the DRAM stack. This structure forms high thermal conductivity heat dissipation paths and provides mechanical constraint. Through 3D finite element analysis (FEA) simulation across 4-dies, 8-dies, 12-dies, and 16-dies stack configurations, we verified the effectiveness of the proposed structure. The proposed package design lowered the maximum package temperature by more than 13% for all stack heights compared to the conventional structures, effectively alleviating thermal hotspots formed at the logic die. Heat flux analysis showed that heat from the logic die was diverted to the sidewall embedded in the EMC region, indicating that previously nonexistent heat dissipation path within the EMC region was created by the new structure. In addition, the average thermal stress at the four corners of the logic die decreased more than 32% for all cases. Simulation results conforms that our proposed design offers a practical path to improve heat dissipation and robustly expands thermal headroom while mitigating corner-dominated thermal stress for high-stacked 3D HBM packages.