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April 30, 2026ACS Applied Electronic Materials2 citations

Integrated ZnO-Based Synaptic Devices to Implement Multiple-Layer Neural Networks on CMOS Circuit Platform for High-Performance Synapse Applications

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YKYong Wook KimInje UniversityYAYeong-Jin AnChungnam National UniversitySKSung-Ho KimChungnam National University

Key Points

  • The aim is to develop high-performance ZnO-based synaptic devices for neuromorphic applications on CMOS technology.
  • Fabricated bilayer HfO2/ZnO and ZrO2/ZnO synaptic devices on an 8-in. CMOS platform.
  • Created a 64 × 64 (4096 devices) 1T1R array chip with DEMUX and input/output circuits.
  • Analyzed synaptic characteristics focusing on variability and long-term potentiation/depression.
  • Achieved ±1.4% variability in selection transistors confirming reliable intrinsic device characteristics.
  • Demonstrated excellent recognition accuracy supported by linearity and symmetry in long-term potentiation/depression.
  • Achieved accuracy comparable to state-of-the-art digital CMOS systems, suggesting improved speed–energy efficiency.

Abstract

ZnO-based synaptic devices employing large-bandgap materials─HfO2/ZnO and ZrO2/ZnO─have been proposed for high-performance synapse applications. In this study, bilayer HfO2/ZnO and ZrO2/ZnO synaptic devices were fabricated on an 8-in. complementary metal-oxide semiconductor (CMOS) integrated circuit platform to address the key challenges of synaptic devices, including their variability, reliability, biological synaptic functions, and integration into neuromorphic chips. A 64 × 64 (4096 devices) one-transistor, one-resistor (1T1R, R: synaptic device) array chip with DEMUX and input/output circuits was fabricated, and the synaptic devices within the array were thoroughly analyzed. Leveraging CMOS technology, the array exhibited ±1.4% variability in selection transistors, confirming that the intrinsic characteristics of the synaptic devices could be evaluated without interference from the selection transistors. Moreover, the bilayer synaptic devices, integrated on 8-in. wafers, demonstrated excellent recognition accuracy, supported by the linearity and symmetry of their long-term potentiation/depression characteristics. Notably, a critical feature for practical utilization in 64 × 64 (4096 devices) 1T1R array chips was achieved by modulating the recognition of input patterns. An analog synaptic device neural network achieved an accuracy comparable to that of state-of-the-art digital CMOS systems, with the potential for major improvements in speed–energy efficiency for high-performance spiking neural network and deep neural network applications.

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Cite This Study

Kim et al. (2026) studied this question.

synapsesocial.com/papers/69f2f1be1e5f7920c6387622https://doi.org/10.1021/acsaelm.5c02491
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