Highly Scaled GaN Complementary Technology on a Silicon Substrate

This article reports on the scaling of GaN complementary technology (CT) on a silicon substrate to push its performance limits for circuit-level applications. The highly scaled self-aligned (SA) p-channel FinFET (a fin width of 20 nm) achieved an <tex-math notation="LaTeX">ID,max </tex-math> of −300 mA/mm and an <tex-math notation="LaTeX">RON </tex-math> of <tex-math notation="LaTeX">27 Ω · </tex-math> mm, a record for metal organic chemical vapor deposition (MOCVD)-grown III-nitride p-FETs. A systematic study on impact of fin width scaling and recess depth in these transistors was conducted. A new SA scaled n-channel p-GaN-gate FET (n-FET) process, compatible with the p-FinFET, demonstrated enhancement-mode (E-mode) n-FETs ( <tex-math notation="LaTeX">LG = 200 </tex-math> nm, <tex-math notation="LaTeX">ID,max = 525 </tex-math> mA/mm, and <tex-math notation="LaTeX">RON=2.9\,\,Ω · </tex-math> mm) on the same epitaxial platform. The p-FETs and n-FETs feature competitive performance in their respective categories and, when taken together, offer a leading solution for GaN CT on a silicon substrate.