High-Level Descriptions of Hardware Accelerators for Sorting Algorithms

Sorting algorithms are among the most employed in computer applications. As increasingly large amounts of information need to be processed efficiently, the need for effective methods to sort data remains a relevant problem in applications involving databases. Hardware accelerators are particularly suitable for processing information with high degree of parallelism. In this article, we present several approaches for sorting data by means of reconfigurable hardware, showing its advantage over microprocessor based solutions. Furthermore, the description of a hardware system described in a high-level programming language is confronted with a traditional system designed with System Verilog.