Construction of Lightweight 6‐Bit and 12‐Bit S‐Boxes With Low Hardware Complexity

In this paper, the design of S‐boxes with low‐area hardware and an acceptable security level is presented. The design focus is on lightweight and secure 6‐bit and 12‐bit S‐boxes based on the construction of large S‐boxes from small S‐boxes. We have developed three 6‐bit S‐boxes and six 12‐bit S‐boxes. To achieve these S‐boxes, we have investigated different structures; eventually, we have achieved the presented structures with suitable security features. The 12‐bit S‐boxes are constructed based on a combination of 6‐bit S‐boxes and bit‐wise XOR operations. The design of 6‐bit S‐boxes aims to achieve a structure that requires the minimum number of logic gates and ensures appropriate security. In the design of the proposed S‐boxes, a balance between hardware consumption and security level is simultaneously considered so that the obtained structures have a low number of required gates, low latency, and a high level of security. Hardware results and security analyses are presented for comparison with other similar works. The maximum nonlinearity parameter obtained for the proposed 6‐bit and 12‐bit S‐boxes is 24 and 1888, respectively. The comparison results show that optimal structures with high security have been developed compared to the existing structures. Therefore, these S‐boxes could be good candidates for use in block ciphers.