Comparative Analysis of Semiconductor Device Architectures for 5-nm Node and Beyond

This letter, for the first time, investigates interactive logic cell schemes and transistor architecture scaling options for 5-nm technology node (N5) and beyond. The proposed novel transistors, such as Hexagonal NanoWire (NW) and NanoRing (NR) architectures, are introduced having higher current drivability and lower parasitic capacitance than conventional NW or NanoSlab devices. The standard cell sizing options, including a 1-fin-per-device version and a 2-fin-per-device design, are systematically evaluated. Each device flavor has multiple vertical stacks when wire-like or slab-like structure is used. Comprehensive transistor and logic cell studies demonstrate that the novel NR is the optimal structure for N5 and beyond.