High-speed vision systems that combine high-frame-rate imaging and highly parallel signal processing enable instantaneous visual feedback to rapidly control machines over human-visual-recognition speeds. Such systems also enable a reduction in circuit scale by using a fast and simple algorithm optimized for high-frame-rate processing [1]. Previous studies on vision systems and chips [1-4] have yielded low imaging performance due to large matrix-based processing element (PE) parallelization [1-3], and low functionality of the limited-purpose column-parallel PE architecture [4], constraining vision-chip applications.
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Yamazaki et al. (2017) studied this question.