Finite State Machine Based Traffic Signal Controller Design using Verilog

This paper presents the design of a traffic light controller using Verilog HDL based on a finite state machine (FSM) approach. The system controls a four-way intersection through a sequence of predefined states, ensuring synchronized and conflict-free traffic signal operation. State transitions are governed by a clock signal with fixed timing intervals, and intermediate yellow states are included for safe switching between directions. The design is verified through simulation using waveform analysis and RTL schematic representation, demonstrating correct functionality and reliable performance.