Design of a 7–16 GHz GaAs Power Amplifier with Adaptive Biasing Technique

In this paper, an adaptive biasing technique for an upper-mid band GaAs power amplifier is proposed. The proposed technique applies an adaptive bias circuit (ABC) to the driver stage (DS). In multistage power amplifier architectures, only the minimal current required to drive the power stage (PS) is typically consumed by the DS. Consequently, the overall current consumption of the amplifier is primarily governed by the substantially larger current consumed by the PS. Therefore, for an equivalent improvement in amplitude-to-amplitude (AM-AM) distortion, a higher power-added efficiency (PAE) is achieved when the ABC is applied to the DS than when it is applied to the PS. The proposed power amplifier is operated over the 7 to 16 GHz frequency range, achieving a small-signal gain of 14 to 16 dB, a PAE of 18 to 28% at the 1 dB compression point, and an output power of 21.5 to 24 dBm.