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May 17, 2026Advanced Functional Materials1 citationsOpen Access

Dual‐Inductive and Programmable Switching: A New Paradigm in Ionic Interface‐Controlled Perovskite Memory

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SKSo‐Yeon KimInstituto de Tecnología QuímicaJBJuan BisquertInstituto de Tecnología Química

Key Points

  • The study aims to develop a stable, programmable halide perovskite memristor that overcomes reliability issues associated with traditional filamentary switching.
  • Constructed a halide perovskite memristor with an ion-modulating layer of 1,4-butanediammonium iodide.
  • Implemented dynamic interfacial barrier modulation for resistive switching.
  • Examined the impact of compliance current and operation velocity on programmable multi-level states.
  • Achieved stable non-filamentary switching with reduced random filamentary growth.
  • Demonstrated highly reproducible bidirectional dual-inductive responses.
  • Successfully controlled programmable multi-level states with significant operational stability.

Abstract

ABSTRACT While halide perovskite (HP) memristors exhibit significant potential for artificial neural networks, their reliance on stochastic filamentary switching severely compromises operational stability. Here, we demonstrate a fully programmable, forming‐free HP memristor that overcomes this intrinsic stochasticity through precise ionic interface engineering. By employing 1,4‐butanediammonium iodide (BDAI 2 ) as an ion‐modulating layer, we construct a structurally rigid, cross‐linked interfacial network strongly anchored to the 3D HP surface, forming the grain boundaries‐modulated barrier switching. The robust ion‐blocking barrier fundamentally suppresses random filamentary growth. Resistive switching (RS) is instead governed by dynamic interfacial barrier modulation, driven by the asymmetric accumulation of mobile ions that electrostatically modulates charge injection. Crucially, this stable non‐filamentary mechanism enables highly reproducible, bidirectional dual‐inductive responses, and distinct non‐zero crossing behaviors. For the first time in an operational HP memristor, we successfully achieved these combined dynamic features. We precisely control programmable multi‐level states governed by compliance current and operation velocity. This defect‐engineered, interface‐driven approach establishes a highly reliable and dynamically controllable paradigm for advanced neuromorphic computing and analog memory architectures.

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Cite This Study

Kim et al. (2026) studied this question.

synapsesocial.com/papers/6a095c5d7880e6d24efe27e8https://doi.org/10.1002/adfm.75888
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