Automated visual inspection for lsi water multilayer patterns by cascade pattern matching algorithm

This paper reports on the defect detection algorithm for the LSI wafer multilayer patterns, together with the result of evaluation. The multilayer patterns are constructed by the exposure after alignment between the wafer pattern and the reticle pattern for each chip. Consequently, the position relation between layers is different even for adjacent chips (interlayer registration error). The developed algorithm compares the gray‐level images of adjacent chips on the wafer and extracts the defect without being affected by the inter‐layer registration error. First, the pattern edge is extracted from the gray‐level image, and the position alignment is executed using the edges. Then, by eliminating the region where gray levels are equal, the regions are extracted for which the position alignment is unsatisfactory. The position alignment is attempted again for that region. This procedure is iterated. When the unmatched region of the pattern edge is sufficiently small, it is decided that the interlayer registration error is absorbed, and the unmatched region is extracted as the defect. An automatic visual inspection system was constructed and evaluated experimentally. As a result, it was verified that the whole chip area can be inspected, and the defect of 0.5 μm or more can be detected in a stable way.