Battery-powered edge-AI devices require nonvolatile computing-in-memory (nvCIM) macros for nonvolatile data storage and multiply-and-accumulate (MAC) operations. High inference accuracy requires MAC operations with high input (IN), weight (W), and output (OUT) precisions. A high energy efficiency <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(EFMAC)</tex> and a short computing latency <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(tAC)</tex> are also required. Most existing silicon-verified nvCIM macros use current-mode signal generation; using current [1]–[3] or hybrid current-voltage readout schemes [4]–[5] for multibit MAC operations to compensate for the small BL -voltage swing and signal margin resulting from the low read-disturb-free voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(VRD)</tex> .
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Hung et al. (2022) studied this question.
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