ASIC Implementation of Associative Memory and Hamming Distance for HDC Application

Brain-inspired Hyperdimensional computing (HDC) emulates the human brain in the way of memorization, association, and reasoning. At its essence, HDC is about comparing and manipulating vectors of large sizes, making it a good candidate for the realm of AI. In the classification task, associative memory (AM) is responsible for finding the best match between classes hypervectors and query hypervector using Hamming distance (HM) approach. This paper proposes a digital design for the hyperdimensional associative memory (HDAM) main functionality. The DHAM architectures search for the nearest HM and can be scaled linearly to any vector dimension. The design space is explored for 2-options, namely sequential (SDHAM), optimized for the low area but has high latency, and parallel one (PDHAM), optimized for low latency but incur high area. Proven industry-standard ASIC design flow with 65nm foundry technology is used to realize both design and report the power, performance, and area (PPA) results. Our experimental results show that the SDHAM implementation enhances the area and energy by 1.6x and 4.023x compared to the PDHAM design at the latency cost of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O(nclasses-1)</tex> . In addition, our results improve the area and energy-delay by 4.6x and 5.6x compared to the state-of-art reports.