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This research aims to develop an efficient serial link that enhances communication between chips in advanced packaging systems.

February 1, 2013

A 0.54pJ/b 20Gb/s ground-referenced single-ended short-haul serial link in 28nm CMOS for advanced packaging applications

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Randomized trial tests a new high-speed link for chip communication, suggesting improvements in efficiency and bandwidth.

This research aims to develop an efficient serial link that enhances communication between chips in advanced packaging systems.
Utilized ground-referenced single-ended signaling for data transmission between chips.
Designed a charge-pump transmitter to optimize power use.
Co-designed a channel that maximizes bandwidth per pin in high-density interconnects.
Achieved a data rate of 20 Gb/s with 0.54 pJ/bit energy consumption.
Demonstrated effective communication across multiple chips with significant bandwidth improvements.
Showed that the approach supports advanced computational architectures in 28nm CMOS.

Poulton et al. (2013) studied this question.

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