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Circuit design analysis demonstrates a 4 Gbps transmitter consuming 2.25 mW in 55 nm CMOS, highlighting minimized common-mode disturbances.
In this paper, the design of 4 Gbps, 2.25 mW Scalable Low-Voltage Signaling (SLVS)-type transmitter is described. The analysis of circuit performance is concentrated on the minimization of common-mode voltage disturbances, while providing satisfactory eye diagram parameters and low power consumption. The edge aligner circuit utilization is proposed in order to minimize the time delay between the input positive and the input negative control voltage of the driver. Moreover, the effectiveness of two methods for driver output impedance correction is evaluated. Special emphasis is put on a reliable transmission path modeling, whose parameters influence an overall transmitter operation. The designed transmitter will be fabricated in 55 nm CMOS technology.
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Kadłubowski et al. (2017) studied this question.
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