An equalizer employs reverse scaling and dual-loop adaptation to achieve a binary data rate of 10 Gbit/s. Realized in 0.13 /spl mu/m CMOS technology, the circuit adapts to traces up to 30 inches on FR4 boards while consuming 25 mW from a 1.2 V supply.
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Gondi et al. (2005) studied this question.
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