Design of CMOS 5 Gb/s 4-PAM transceiver frontend for low-power memory interface

A 5Gb/s four-level pulse amplitude modulation (4-PAM) transceiver front-end for low-power memory interface is proposed. Since the most power-consuming blocks in high-speed link front-end are drivers, and equalizers, in this work, we have used 4-PAM voltage mode driver to reduce the power consumption of driver and equalizer. Moreover, an analysis to minimize voltage mode driver power consumption is presented. In order to eliminate the reflection in a multi-drop bus, an impedance-matched bi-directional multi-drop bus has implemented. Simulation results show the proposed transceiver front-end has power efficiency of 1.7 mW/Gbps. Circuit design and simulation were done in 0.13-µm CMOS technology.